The present invention relates to multiprocessor computer systems, and more particularly to multiprocessor computer systems implementing techniques for reducing bus contingency issues.
In a computer system, a bus is the means by which the electrical signals are communicated back and forth between a central processor, memory, and other devices such as input and output adapters. In a uniprocessor computer system, the bus may simply be a plurality of electrical conductors linking the various components of the system. However, in multiprocessor and other more sophisticated computer systems, the bus may become more complex and play an active role in directing the various signals between the components of the computer system, usually for the purpose of obtaining greater data throughput or speed of operation.
One of the significant restrictions in the operation of a modern high speed computer is the memory access time of main memory. The memory access time is the time required for the memory to retrieve the information from its internal storage after it has received a read address signal. Since a high percentage of data processing activities in a computer system involves reading information from memory, the cumulative amount of memory access time involved in typical data processing activities can be significant. The cumulative effect of the waiting during access time periods is to reduce the data throughput of the computer system. In a uniprocessor computer system, this is not a problem because there is nearly nothing else which the system could be doing during the access time period. However, in multiprocessor systems, the other processors in the system could use the access time periods to conduct other activities through the bus, and thereby increase the efficiency of the system.
The bus that has the above-mentioned problems is called a single transaction bus. When a master device (e.g. processor) requests data from a target device (e.g. memory) through the bus, the bus is unavailable for use by any other devices until the requested data is returned to the requesting master device. This bus is called a single transaction bus because the entire transaction between two devices through the bus must complete before another transaction starts through the bus. Therefore, if the target device is slow in retrieving requested data, the bus is blocked and unused for a very long time.
This problem has been recognized and, as a result, split transaction buses have been devised. In a split transaction bus, the master device obtains bus use permit from a bus arbiter and sends a read command (a request for data) through the bus to the target device and then releases the bus for use by other devices. The target device, after receiving the read command, retrieves the requested data from its internal memory and then obtains bus use permit from the bus arbiter. After getting the permit, the target device sends the requested data to the requesting master device. This bus is called a split transaction bus because the transaction between the master and target devices is split in time into two transactions so that during the time in between the bus is free for use by other devices. Write transaction are still single transactions in this split transaction bus. In a write transaction, the master device sends a write command followed by write data through the bus to the target device. When the target device signals the receipt completion, the master device releases the bus.
This split transaction bus still has problems. If the target device receives a read command through the bus from a master device A and then, when it (target device) is busy retrieving the requested data from its internal memory, another transfer command (a read or a write command) comes to it through the bus from a second master device B, the target device must returns a busy signal so that master device B can resend the transfer command later. This causes the following problems. First, it costs bus time to send busy signals from the target device through the bus to master device B. This may occur more than once because at the next attempt by master device B, the target device may still be busy. Second, it also costs bus time to resend the transfer command from master device B through the bus to the target device. These two problems can be more significant when many master devices send transfer commands to the busy target device and all of them have to repeatedly resend their transfer commands. Third, the order of execution of transfer commands is not optimal, i.e. not first come first served.
Therefore, an object of the present invention is to provide a multiprocessor computer system in which there is no waste of bus time for sending busy signals from target devices to master devices.
Another object of the present invention is to provide a multiprocessor computer system in which there is no waste of bus time for resending transfer commands from master devices to target devices.
Yet another object of the present invention is to provide a multiprocessor computer system in which the transfer commands from master devices to a target device are executed by the target device in a first come first serve order.
The present invention achieves the stated objects by providing a FIFO (first in first out) buffer for each target device in the multiprocessor computer system. Transfer commands from master devices through the bus to a target device will be put in the FIFO of the target device in the order of their arrival. The transfer command will be taken out of the FIFO and be executed by the target device in the same order. Write transactions are still single transactions, i.e. in a write transaction, the write command and write data both are sent from the master device through the bus and put in the FIFO of the target device. The target device will take the write command and write data from the FIFO and execute the write command. In a read transaction, the read command is sent from the master device through the bus to the FIFO of the target device. Later, this read command is taken out from the FIFO and executed by the target device, and requested data is sent from the target device through the bus to the requesting master device. If the FIFO is sufficiently deep, all incoming transfer commands will be put in the FIFO for later execution by the target device. Therefore, there is no waste of bus time related to transfer commands being rejected.